Semiconductor device comprising a field-effect transitor and method of operating the same

ABSTRACT

The invention relates to in particular a lateral DMOST with a drain extension ( 8 ). In the known transistor a further metal strip ( 20 ) is positioned between the gate electrode contact strip and the drain contact ( 16 ) which is electrically connected with the source region contact ( 15 ). In the device proposed here, the connection between the further metal strip ( 20 ) and the source contact ( 15,12 ) comprises a capacitor ( 30 ) and the further metal strip ( 20 ) is provided with a further contact region ( 35 ) for delivering a voltage to the further metal strip ( 20 ). In this way an improved linearity is possible and the usefulness of the device is improved in particular at high power and at high frequencies. Preferably the capacitor ( 30 ) is integrated with the transistor in a single semiconductor body ( 1 ). The invention further comprises a method of operating a device ( 10 ) according to the invention.

The invention relates to a semiconductor device comprising asemiconductor body which is provided with a field effect transistor at asurface and which comprises strongly doped source and drain zones and achannel region extending between the source zone and the drain zone,with a gate electrode being present which overlaps the channel regionupon perpendicular projection thereon, wherein the source zone, thedrain zone and the gate electrode are connected at the surface to ametal source contact, a drain contact and a gate electrode contact,respectively, and wherein a further metal strip is positioned betweenthe gate electrode contact and the drain contact, which metal strip isinsulated from the semiconductor body, is locally electrically connectedto the source strip and forms a shield between the gate electrode andthe drain contact. Such a device may be used to advantage as a (high)power amplifier, in particular for a transmitter in the high-frequencyrange of wireless communication. The presence of the shield between thegate electrode contact and the drain contact leads to a significantcapacity reduction between the drain contact and the gate electrode,which in turn leads to a significant power amplification increase athigher frequencies.

Such a device, which may be constructed both in discrete and inintegrated form, is known from U.S. Pat. No. 6,069,386, which waspublished on 30 May 2000. The known device comprises a lateral metaloxide semiconductor-type transistor. The transistor is formed in aweakly doped p-type epitaxial layer on a strongly doped p-typesubstrate. The channel is defined in a p-type zone which is implantedinto the epitaxial layer in a self-aligned manner with respect to thepolycrystalline silicon gate electrode. The source and drain zones mayhave an interdigitated structure, the number of digits being chosen, forexample, in dependence on the maximum electric current to beaccommodated. The drain extension serves to increase the breakdownvoltage between source and drain, as is generally known. Since the metalsource contact is not arranged above but beside the gate electrode, thegate electrode can be provided with a metal connection over its entirelength, so that the gate resistance is determined by the layerresistance of the metal, and accordingly it can be kept very low throughthe use of a suitably conductive metal. The contacts are in the form ofparallel metal strips arranged side by side. Since the further metalstrip and the metal contact of the gate electrode can be manufactured inthe same metal layer as the source and drain contacts, relatively fewprocess steps are necessary for the manufacture thereof.

One drawback of the known device is the fact that it does not have alinear characteristic, in particular at very high frequencies. As aresult, the maximum usable power is limited.

Accordingly, the object of the present invention is to provide a deviceof the kind referred to in the introduction, which is highly linear,also at high frequencies, and which is capable of providing a high powerlevel.

According to the invention, a semiconductor device of the kind referredto in the introduction is characterized in that the electricalconnection between the further metal strip and the source contactcomprises a capacitor, and in that the further metal strip is providedwith a connecting contact for applying an external voltage to thefurther metal strip. The invention is in the first place based on therecognition that the provision of a capacitor in the connection betweenthe further metal strip and the contact source enables the applicationto the further metal strip of a voltage which is different from thevoltage of the source region. In order to enable the application of sucha voltage to the further metal strip, said metal strip is according tothe invention provided with a connecting contact. The invention isfurthermore based on the recognition that the linearity of the devicecan be significantly improved by applying such a voltage to the furthermetal strip. This is based on the recognition that the device accordingto the invention may be considered to comprise two field effecttransistors, namely a first enhancement-type transistor, which isassociated with the gate electrode, and a second depletion-typetransistor, whose further metal strip forms the gate electrode, as itwere. Since the former transistor operates in the so-termed commonsource configuration in the device according to the invention, and thelatter transistor operates in the so-termed common gate configuration,the two transistors operate in a cascade (=series connected)configuration and exhibit opposite phase distortion which enables phaseextinction and thus less distortion. Said further contact region makesit possible, through the application of an external voltage, to set thepower level at which the aforesaid extinction takes place. This enablesoptimization of the linearity in dependence on the selected use of thedevice.

The capacitor may be externally connected to the device. A device whichis ready for use is normally provided with an insulating envelope ofplastic material, from which a number of terminal pins, four terminalpins in an advantageous embodiment of a device according to theinvention, extend. The capacitor may be bonded to the enveloped device,for example, and be connected to the terminal pins for the source regionand for the further metal strip.

In an advantageous embodiment, the capacitor is integrated in thesemiconductor body and is positioned within the active region beside thetransistor. Such a device is easy and inexpensive to manufacture.Preferably, the source contact, the drain contact, the gate electrodecontact, the further metal strip and the connecting contact thereof andan electrode of the capacitor are formed of two separate metal layersarranged one above the other, which are separated from each other by afurther insulating layer.

Such a two-metal layer process makes it possible to connect the furthermetal strip to the (one) electrode of the capacitor at severalpositions, which connections cross the gate electrode contact. The useof a large number of such connections is advantageous with a view tolowering the impedance for the operating frequency between the furthermetal strip and the capacitor electrode. Another important aspect ofsuch a two-metal layer process is the fact that two adjacent gateelectrode digits may be connected via the upper layer of the two metallayers. Each digit may be connected to a conductor track in the uppermetal layer by means of a conducting via. In that case a conductingdigit will be present—in the upper metal layer—between two adjacent gateelectrodes, to which digits the conductor tracks of the two adjacentgate electrodes that lead to a via are connected. The conducting digitis connected to the contact region for the gate electrode, crossing theunderlying source contact, which is interrupted at the location of saidcrossing so as to reduce the capacity. Preferably, two adjacent gateelectrodes are connected to the conducting digit at several positions inthis manner. For technical reasons, each gate electrode is preferablywidened at the location of said connection. The advantage of such aconnection of the gate electrode to the gate electrode connecting regionis that the connecting resistance of the gate electrode may be low,whereas the width thereof may nevertheless be relatively small.Preferably, in order to reduce said resistance, the polycrystallinesilicon of the gate electrode, too, has been partially converted into asilicide, such as a titanium silicide.

In another variant, the other electrode of the capacitor is formed bythe semiconductor body, which comprises a strongly doped substrate, onwhich a more weakly doped epitaxial layer is present. The substrate isconnected to a metal layer, which also forms a connection for the sourceregion.

In an advantageous variant, the two electrodes of the capacitor formpart of the metal layers, and the lower electrode of said two electrodesis electrically connected to the semiconductor body, which comprises astrongly doped region at that location. In this way avoltage-independent operation of the capacitor can readily be realized,which is advantageous. In this case silicon nitride may be used as thedielectric of the capacitor. Another advantage of such a capacitor isthe fact that a higher capacity per unit area can be achieved, thusenabling a reduction of the surface area that is taken up by a capacitorhaving a given capacity. The strongly doped region comprises, forexample, the substrate and a more strongly doped (by means of a localdiffusion) portion of a (more weakly doped) epitaxial layer present onthe substrate.

The capacitance of the capacitor partially depends on the desiredfrequency. Preferably it ranges between 10 pF and 1 nF at an operatingfrequency ranging between 100 MHz and 3 GHz. Since a device according tothe invention can be used with higher power levels than the prior artdevice, a device according to the invention is preferably provided witha heat sink, which preferably comprises copper and/or tungsten-copperparts.

The invention may be used to advantage in (n-channel or p-channel)transistors, in which the channel is formed by a surface region of thesemiconductor body, and in which the channel is separated from the gateelectrode by means of an electrically insulating layer. A preferredembodiment of a device according to the invention is characterized inthat the transistor is of the lateral DMOS type, in which D stands for“double diffused”. The invention is also suitable for use in othertransistors, however, such as MESFET's, and in particular HEMT's, whichare based on a semiconductor body of a III-V material, such as GaAs orGaN. Furthermore it is advantageous if a heat sink is present on theside of the semiconductor body remote from the surface.

Preferably, a minimum spacing is used between the further metal stripand the gate electrode contact. This makes it possible to influenceother characteristics of the transistor as well via the voltage on thestrip. Preferably, this takes place in an independent manner, withanother metal strip—which is likewise insulated from the semiconductorbody—being present between the further metal strip and the gateelectrode, which other strip is connected in the same manner as in theprior art device, for example. Said other strip may furthermore beconnected in the same manner as the further metal strip in the deviceaccording to the invention. In that case the other transistorcharacteristics can be influenced through the application of a differentexternal voltage to the other metal strip, independently of the voltagebeing applied to the further metal strip.

The invention furthermore comprises a method of operating a deviceaccording to the invention, in which a voltage is applied to the contactregion of the further metal strip during operation of the device. Theapplied voltage may be dynamically controlled, that is, the voltage thatis applied in the higher power region is different from the voltage thatis applied in the lower power region. According to another possibility,a gradually changing, power-dependence voltage is advantageouslyapplied. In this variant, use is preferably made of the capacitor thatis entirely formed in the two metal layers. Such a capacitor can be moreeasily connected to a circuit that is integrated in the device, by meansof which a specific voltage function can be applied.

The above and further aspects of the invention will now be explained inmore detail by means of an embodiment. In the drawing:

FIG. 1 is a top plan view of a semiconductor device according to theinvention;

FIG. 2 is a top plan view of an enlarged portion, indicated II in FIG.1, of the device of FIG. 1;

FIG. 3 is a sectional view of this device along the line III-III;

FIG. 4 is a sectional view of this device along the line IV-IV;

FIG. 5 is a sectional view of a variant of this device along the lineIII-III;

FIG. 6 shows magnitudes illustrating the amplitude and phase linearityof the device of FIG. 1 as a function of the input power;

FIG. 7 shows a distortion factor and the amplification of the device ofFIG. 1 as a function of the average power;

FIG. 8 shows two the distortion factors and the efficiency of the deviceas a function of the average power.

It is noted that the drawing is merely diagrammatic and not drawn trueto scale. It is further noted that the metallization pattern is mainlyshown in FIG. 1 and FIG. 2. Parts which lie at a lower level are notshown in FIG. 1 and FIG. 2, but only in the sectional views of FIG. 3,FIG. 4 and FIG. 5 for the sake of clarity. As regards the centralportion of FIG. 1, a detail view as shown in FIG. 2 provides a betterunderstanding of the interdigitated structure of the transistor.

The device (see FIGS. 1-4) comprises a semiconductor body 1, which ismade of silicon in this example, but which may also be made of anothersuitable semiconductor material, of course. It is provided with aninsulating layer 76 of silicon dioxide. The semiconductor body is builtup of a low-ohmic, strongly doped p-type substrate 2 and a comparativelyweakly doped, high-ohmic region 3 adjoining the surface of the siliconbody, in which the transistor is accommodated. In this example, theregion 3 is formed by a p-type epitaxial layer having a thickness ofapproximately 7 μm and a doping concentration of approximately 5.10¹⁵atoms per cm³. The doping concentration of the substrate 2 whichfunctions as a connection for the source zone is high, for examplebetween 10¹⁹ and 10²⁰ atoms per cm³. An active region 6 is defined inthe epitaxial layer, which region is laterally bounded by thick fieldoxide 7. Source and drain zones of the transistor are provided in theactive region in the form of strongly doped n-type surface zones 4 and5, respectively. The transistor comprises a multi-digit structurecomprising a number of source/drain digits lying beside one another,which are only shown schematically (FIG. 1) or in part (FIG. 2) in thedrawing. The multi-digit structure may be obtained in a simple manner,for example by extending the portion that is shown in FIG. 3 to the leftand to the right until the desired channel width is obtained. Toincrease the breakdown voltage, the drain zone 5 is provided with ahigh-ohmic n-type drain extension 8 between the drain zone 5 and thechannel of the transistor. The length of the extension is 3.5 μm in thisexample. The transistor channel is formed by the p-type region 13between the extension 8 and the source zone 4. A gate electrode 9 isprovided above the channel, which gate electrode is separated from thechannel by a gate oxide 10 having a thickness of, for example, 70 nm.The gate electrode 9 is formed by strips of strongly doped,approximately 0.3 μm thick polycrystalline silicon (poly) overlaid withapproximately 0.2 μm titanium silicide, which, seen at the surface,extends transversely over the active region 6 between the source zones 4and the drain extensions 8. The source zone (or zones) 4 is (are)short-circuited with the p-type region via a deep, strongly doped p-typezone 11 which extends from the surface down to the strongly dopedsubstrate and which connects the source zone 4 to the source electrode12 at the lower side of the substrate via the substrate 2. Thetransistor is embodied as an LDMOST, so that it can be operated at asufficiently high voltage, for which purpose an additional p-type dopingis provided in the channel in the form of the diffused p-type zone 13,so that the doping concentration is locally increased as compared withthe weak epi doping.

The surface is coated with a thick glass layer, in which contact windowsare provided above the source and drain zones, through which windows thesource and drain zones are connected to metal source and drainelectrodes 15 and 16, respectively. As is apparent from the plan view ofFIG. 2, the contacts 15 and 16 are formed by metal strips extendingparallel to each other over the glass layer. The source contact 15 isnot only connected to the source zone(s), but also to the deep p-typezone 11, and thus interconnects the source zone and the connection 12 atthe bottom side of the substrate. The source zone may be connected toexternal connections via this connection. The drain electrode strips 16(FIG. 1) form a comb structure together with the base portion 17, theymay be connected to a number of bond pads 116 present elsewhere on thecrystal via the common portion 17.

The gate electrode 9 of the device is also provided with a metalcontact, which extends in the form of a strip 118 over the oxide layerbetween the metal strips 15 and 16, and which is locally connected tothe gate 9 via contact windows in the oxide layer. The metal track 18 isnot connected to the gate 9 over its entire length, but only in a numberof interspaced locations, at which the poly gate 9 is provided withwidened portions suitable for connections 19, only one of which—for eachgate electrode 9—is shown. If the interspacings between the connections19 are sufficiently small, the gate resistance is significantly reducedby the presence of the metal tracks 118. The resistance of the gateelectrode is also reduced by the presence of titanium silicide thereon.A very low gate resistance can be obtained through the use of a metalhaving a low resistivity, for example gold or aluminum. As is shown inFIG. 2, the polysilicide (in this example) track of the gate electrodehas a comb shape which forms an interdigitated structure with the drainelectrode 16, 17. The base of the comb of the gate electrode metaltracks 118 is a metal strip 40, which is provided with evenly spacedbond pads 45 for the gate electrode 9. Adjacent gate electrodes 9 areinterconnected, for example in three places—only one of which is shownin FIG. 1—at the location of connections (not shown in the figure) ofthe gate electrode 9. In that case a metal track 118, which is connectedto the base portion 40 of the gate electrode, extends centrally oversaid connections. The metal strip 15 of the source region 4 isinterrupted at the location of said track 118 so as to reduce thecapacitance with the track 118.

Further metal tracks 20 are provided between the polysilicide tracks 18of the gate electrode 9 and the Al tracks 16 of the drain contact. Saidtracks 20 are connected to an electrode 31 of a capacitor 30 and also toa connecting bond pad 35, where an external voltage is applied duringoperation of the device 10. The (partially interconnected) shieldingtracks 20 are connected to the capacitor 30 at evenly spaced positions,said tracks being formed in the lower layer of the two metal layers20,18 that are separated from each other by means of an insulatingsilicon dioxide layer 77. The use of a two-metal layer process makes itpossible for the metal tracks 22 to cross the gate electrode 9,18. Thismakes it possible to connect metal tracks 20 having a minimumresistivity. In this example, another electrode of the capacitor 30 isformed by the portion of the semiconductor body 1 that is present undera thin oxide layer 36, in this case a portion of the epitaxial layer 3and the substrate 2, which electrode is connected to the sourceconnection 12, therefore. The upper electrode 31 is connected, via metalplugs 34 and an additional metal layer 37 incorporated therein, to apolycrystalline silicon region 99 present on the oxide layer 36 and tothe further metal strip 20. In this example, the capacity is 100 pF.

According to the invention, distortion compensation may occur uponpresentation of an external voltage to the contact region 35 in thedevice 10 of this example, owing to the fact that the device comprisestwo transistors, as it were, an enhancement-type transistor and adepletion-type transistor. As a result, the device exhibits an improvedlinearity and operation at higher power levels is possible in comparisonwith the prior art device. It has been found that a suitable externalvoltage on the metal tracks 20 is about +25 V. All this will beillustrated hereinafter in the discussion of FIGS. 6-8.

In a very advantageous variant of the device 10 discussed herein (seeFIG. 5), use has been made in the forming of the capacitor 30 of thefact that the device has been formed by means of a two-metal layerprocess. The lower electrode 32 is formed in the first (lower) metallayer, whilst the upper electrode 31 is formed in the second (upper)metal layer. Present between the two layers is a dielectric of, forexample, silicon nitride having a thickness of 100-500 nm. The lowerelectrode 32 is connected, via metal plugs 34 in an insulating layer, toa silicide region 35 at the surface of the semiconductor body 1, whichis further provided with a strongly doped (p-type) semiconductor region36 at that location. The main advantages of this variant are the factthat a higher capacity value per unit area is possible, and thatconsequently the surface area of the capacitor 30 may be smaller. Thecapacity of the capacitor 30 is further substantially independent of thevoltage. A final advantage is the fact that the capacitor 30 can easilybe connected as a series capacitor, via the lower electrode 32, to acircuit (preferably integrated therewith) capable of applying apower-dependent voltage, for example, to the metal tracks 20. Thisenables a further improvement and optimization of the distortion andthus use of the device at even higher power levels.

FIG. 6 shows the magnitude S21 as a function of the input power. Thiscomplex magnitude S21 is also known as the large signal transducer gain,and it characterizes the linearity of a device, in this case the deviceof FIG. 1. The large signal gain S21 is defined as the ratio between theforward wave at the output and the forward wave at the input and can berepresented as r.e^(i*φ). In the figure, the upper group of curves 60represent the normalized argument (ArgS21) of S21, and the lower groupof curves 61 represent the magnitude (Mag 21) of S21 as a function ofthe input power Pin. The drain-source voltage Vds is 26 V, and thefrequency f is 2 GHz. The curves 61 a-61 e and 60 a-60 e show thechanges in a voltage on the further metal tracks 20, which changes takeplace in steps (step size is 10 V) from +20 V to −20 V. The magnitudeMagS21 only depends on the voltage on the metal tracks 20 to a smallextent. The magnitude ArgS21, however, exhibits a strongly improvedprofile (curve 60 a) for a voltage of +20 V on the aforesaid metaltracks 20. The (phase), distortion of a device according to theinvention—during operation—has been significantly improved in comparisonwith the prior art device, therefore.

FIG. 7 shows a distortion characterizing factor and the gain of thedevice of FIG. 1 as a function of the average power. The upper group ofcurves 70 represent the gain Gp as a function of the average power Pavand the lower group of curves 71 represent the intermodulationdistortion IMD3 for a two-tone system, wherein f1=2,000 GHz and f2=2,001GHz. Vds is likewise 26 V, and the voltage on the gate electrode 9 is4.70 V. The curves 70 a-70 j and 71 a-71 j represent the changes in avoltage on the further metal tracks 20, which changes take place insteps (step size is 5 V) from +25 V to −25 V. The influence of theaforesaid voltage on the gain Gp is small. A significant improvement ofIMD3—at higher power levels—is realized, however, when the aforesaidvoltage is approximately +25 V.

FIG. 8 shows two distortion factors and the efficiency of the device asa function of the average power. A two-carrier WCDMA (=Wideband CodeDivision Multiple Access) system is concerned here. Curve 80 arepresents the efficiency (Eff) for a voltage on the metal tracks 20 of+25 V, whilst said voltage is 0 V for the curve 80 b. The aforesaidvoltage has practically no effect on the efficiency, therefore. Thecurves 81 a and 81 b represent the ACPR (=Adjacent Power Ratio) for ametal strip 20 voltage of +25 V and 0 V, respectively. The curves 82 aand 82 b represent the magnitude IM3 for corresponding voltages on thefurther metal strip 20. FIG. 8 shows that the distortion characterizingmagnitudes ACPR and IM3 improve significantly at high power levels for atwo-carrier system, too, for a voltage on the further metal strip 20 of+25 V. This figure also illustrates that it may be useful to make theaforesaid voltage dependent on the power level. Thus, the aforesaidvoltage may be lower at lower power levels than at higher power levels.The change may take place in steps or continuously, and in both cases itmay be applied by a circuit which has been added to the device and whichis preferably integrated therewith.

It will be apparent that the invention is not limited to the embodimentdescribed herein, but that many more variations are possible to thoseskilled in the art within the scope of the invention. Thus the inventionmay also be used to advantage in p-channel MOS transistors. Theinvention may furthermore be used not only in DMOS-type transistors, butalso in MOS transistors in which the channel is formed by a surfaceregion of the epitaxial layer 3, possibly with additional Vtimplantation, instead of a diff-used zone. Furthermore it is possible touse the invention in transistors of the so-termed VDMOS type, wherein Vstands for vertical, and wherein the channel and the gate electrodestill extend (at least substantially) parallel to the surface of thesemiconductor body, indicated by the term “semi-lateral” in the presentapplication. Although use in truly vertical MOS transistors, in whichthe channel and the gate electrode extend substantially perpendicularlyto the surface of the semiconductor body, for example in/on the sidewall of a groove in said surface, is in itself conceivable, such use isnot practically feasible, given the present state of the technology.

Although the device according to the invention preferably comprises asilicon semiconductor body, the invention may also be used in devicesmade of other semiconductor materials, such as GaAs or other so-termedIII-V materials.

It is further noted that while mention is only made of a discretesemiconductor element in the embodiment described herein, the inventionis also suitable for the manufacture of other integrated semiconductorproducts, which may comprise a larger number of active semiconductorelements.

It is further noted that the transistor may be used to great advantagein the 0.5-5 GHz range, in particular in the 0.9-2.4 GHz range, withinwhich range the major frequency bands for mobile communication lie, andthat it is suitable for power amplification at lower and also at highersource-drain voltages, such as 20-30 V, for example.

1. A semiconductor device comprising a semiconductor body which isprovided with a field effect transistor at a surface and which comprisesstrongly doped source and drain zones and a channel region extendingbetween the source zone and the drain zone, with a gate electrode beingpresent which overlaps the channel region upon perpendicular projectionthereon, wherein the source zone, the drain zone and the gate electrodeare connected at the surface to a metal source contact, a drain contactand a gate electrode contact, respectively, and wherein a further metalstrip is positioned between the gate electrode contact and the draincontact, which metal strip is insulated from the semiconductor body, islocally electrically connected to the source strip, and forms a shieldbetween the gate electrode and the drain contact, characterized in thatthe electrical connection between the further metal strip and the sourcecontact comprises a capacitor, and in that the further metal strip isprovided with a connecting contact for applying an external voltage tothe further metal strip.
 2. A semiconductor device as claimed in claim1, characterized in that the capacitor is integrated in thesemiconductor body and is positioned within the active region beside thetransistor.
 3. A semiconductor device as claimed in claim 2,characterized in that the source contact, the drain contact, the gateelectrode contact, the further metal strip and the connecting contactthereof, and an electrode of the capacitor are formed from two separatemetal layers arranged one above the other, and separated from oneanother by a further insulating layer.
 4. A semiconductor device asclaimed in claim 3, characterized in that the other electrode of thecapacitor is formed by the semiconductor body, which comprises astrongly doped substrate on which a more weakly doped epitaxial layer ispresent.
 5. A semiconductor device as claimed in claim 3, characterizedin that the two electrodes of the capacitor form part of the metallayers, and the lower electrode of said two electrodes is electricallyconnected to the semiconductor body, which comprises a strongly dopedregion at that location.
 6. A semiconductor device as claimed in claim1, characterized in that the capacitance value of the capacitor rangesbetween 10 pF and 1 nF at an operating frequency ranging between 100 MHzand 3 GHz.
 7. A semiconductor device as claimed in claim 1,characterized in that the field effect transistor is a MOS transistor,in which the semiconductor body comprises a comparatively weakly dopedregion of a first conductivity type adjoining the surface, which regionis provided with the strongly doped source and drain zone of theopposed, second conductivity type and a weakly doped drain extensionbetween the drain zone and the channel region, wherein the gateelectrode is electrically insulated from the channel region and anelectrically insulating layer is laid over the surface, which layer isprovided with contact windows above the source zone, the drain zone andthe gate electrode, through which contact windows the source zone, thedrain zone and the gate electrode, respectively, are connected to thecontacts.
 8. A semiconductor device as claimed in claim 1, characterizedin that said contacts are embodied as parallel metal strips positionedbeside each other.
 9. A semiconductor device as claimed in claim 1,characterized in that another metal strip is present between the furthermetal strip and the gate electrode, which other strip is separated fromthe semiconductor body by an electrically insulating layer and may ormay not be provided with another connecting contact for applying anotherexternal voltage.
 10. Method of operating a semiconductor device asclaimed in claim 1, wherein a voltage is applied to the contact regionof the further metal strip during operation of the device.
 11. A methodas claimed in claim 10, characterized in that the applied voltage isselected independence on the power range within which the deviceoperates.